Programming FLASH-memory chips. Memory chips Writing to a memory chip

The need for non-volatile flash memory is growing in proportion to the degree of advancement of computer systems into the field of mobile applications. Reliability, low power consumption, small size and light weight are the obvious advantages of flash media compared to disk drives. Given the ever-decreasing cost of storing a unit of information in flash memory, media based on it provide more and more advantages and functionality to mobile platforms and portable equipment using flash memory. Among the variety of memory types, NAND flash memory is the most suitable basis for building non-volatile storage devices for large amounts of information.

Currently, there are two main structures for building flash memory: memory based on NOR cells and NAND. The NOR structure (Fig. 1) consists of elementary information storage cells connected in parallel. This organization of cells provides the possibility of random access to data and byte-by-byte recording of information. The NAND structure (Fig. 2) is based on the principle serial connection elementary cells forming groups (16 cells in one group), which are combined into pages, and pages into blocks. With such a construction of a memory array, access to individual cells is impossible. Programming is carried out simultaneously only within one page, and when erasing, access is made to blocks or groups of blocks.

fig.1 NOR structure fig.2 NAND structure

As a result, the differences in structure organization between NOR and NAND memory are reflected in their characteristics. When working with relatively large data arrays, the write / erase processes in NAND memory are performed much faster than NOR memory. Since 16 adjacent NAND memory cells are connected in series with each other without any contact gaps, a high cell area on a chip is achieved, which allows obtaining a large capacity at the same technology standards. At the core of NAND flash programming is the process of electron tunneling. And since it is used for both programming and erasing, low power consumption of the memory chip is achieved. The sequential cell structure allows for a high degree of scalability, making NAND flash a leader in the memory expansion race. Because electron tunneling occurs across the entire cell channel area, NAND flash has a lower charge capture rate per unit area than other flash technologies, resulting in a higher program/erase cycle rate. Programming and reading is performed sector by sector or page by block, in blocks of 512 bytes, to emulate the common sector size of disk drives.

The main differences in the parameters of flash memory manufactured using different technologies are shown in Table 1.

Table 1. Comparative characteristics of memory modules based on NAND and NOR cells

Parameter NAND NOR
Capacity ~ 1 Gbps (2 dies per package) ~ 128 Mbps
Supply voltage 2.7 - 3.6 V 2.3 - 3.6 V
Input Output x8 / x16 x8 / x16
Access time 50 ns (sequential access cycle)
25 µs (random access)		 70 nS (30 pF, 2.3 V)
65 nS (30 pF, 2.7 V)
Programming speed (typical) -
200 µs / 512 bytes		 8 µs/byte
4.1 ms / 512 bytes
Erase speed (typical) 2 ms/block (16 kB) 700ms/block
Aggregate speed
programming and erasing (typical)		 33.6 ms / 64 kB 1.23 sec/block (Main: 64 kB)

The leading leader in the production of NAND-flash chips is Hynix. It produces several varieties of memory chips, differing in the following key parameters:

  • capacity (256 Mbps, 512 Mbps and 1 Gbps);
  • bus width, 8 or 16 bits (x8, x16);
  • supply voltage: 2.7 to 3.6 V (3.3 V devices) or 1.7 to 1.95 V (1.8 V devices);
  • page size: in x8 devices (512 + 16 spare) bytes, in 16x - (256 + 8 spare) words;
  • block size: in x8 devices (16K + 512 spare) bytes, in 16x - (8K + 256 spare) words;
  • access time: random access 12 µs, sequential 50 ns;
  • page programming time 200 µs;

All Hynix NAND flash chips feature a typical 2ms block erase time, hardware power transient data protection, and 100,000 write/erase cycles. Guaranteed data retention time is 10 years. An important feature of Hynix memory chips is their pin-to-pin compatibility regardless of capacity. This makes it very easy to improve the consumer characteristics of the final product. Table 2 shows the basic parameters of all Hynix NAND flash chips.

Table 2. Comparative list of Hynix NAND flash chips

Volume Type Organization Voltage
nutrition		 Range
workers
temperatures * 		speed
(ns)		 Frame
256Mbit 32Mx8 1.8V C,E,I 50 TSOP/WSOP/FBGA
32Mx8 3.3V C,E,I 50 TSOP/WSOP/FBGA
16Mx16 1.8V C,E,I 50 TSOP/WSOP/FBGA
16Mx16 3.3V C,E,I 50 TSOP/WSOP/FBGA
512Mbit 64Mx8 1.8V C,E,I 50 TSOP/WSOP/FBGA
64Mx8 3.3V C,E,I 50 TSOP/WSOP/FBGA
32Mx16 1.8V C,E,I 50 TSOP/WSOP/FBGA
32Mx16 3.3V C,E,I 50 TSOP/WSOP/FBGA
1Gb 128Mx8 1.8V C,E,I 50 TSOP/WSOP/FBGA
128Mx8 1.8V C,E,I 50 TSOP/WSOP/FBGA
128Mx8 3.3V C,E,I 50 TSOP/WSOP/FBGA
128Mx8 3.3V C,E,I 50 TSOP/WSOP/FBGA
64Mx16 1.8V C,E,I 50 TSOP/WSOP/FBGA
64Mx16 1.8V C,E,I 50 TSOP/WSOP/FBGA
64Mx16 3.3V C,E,I 50 TSOP/WSOP/FBGA
64Mx16 3.3V C,E,I 50 TSOP/WSOP/FBGA

* - Temperature ranges
C- Commercial operating temperature range 0...+70°C
E- Extended operating temperature range -25...+85°C
I- Industrial operating temperature range -40...+85°C

In more detail, the features of Hynix memory chips can be considered using the example of crystals of the HY27xx(08/16)1G1M series. Figure 3 shows the internal structure and pin assignment of these devices. Address lines are multiplexed with data I/O lines on an 8 or 16 bit I/O bus. Such an interface reduces the number of pins used and makes it possible to move to higher capacity chips without changing the PCB. Each block can be programmed and erased 100,000 times. Error Correction Code (ECC) is highly recommended to extend the life cycle of NAND flash devices. The ICs have an open drain read/busy output that can be used to identify PER (Program/Erase/Read) controller activity. Since the output is open-drain, it is possible to connect several such outputs from different memory chips together through one "pull-up" resistor to the positive terminal of the power supply.


Fig.3 Internal organization of Hynix NAND flash chips

For optimal work with defective blocks, the "Copy Back" command is available. If the programming of a page fails, the data for this command can be written to another page without resending it.

Hynix memory chips are available in the following packages:

  • 48-TSOP1 (12x20x1.2 mm) - fig.4;
  • 48-WSOP1 (12x12x0.7 mm)
  • 63-FBGA (8.5x15x1.2mm, 6x8 ball array, 0.8mm pitch)


Fig.4 Hynix NAND Flash

The NAND memory array is organized in blocks, each containing 32 pages. The array is divided into two areas: main and spare (Fig. 5). The main area of ​​the array is used to store data, while the spare area is usually used to store error correction codes (ECC), software flags, and bad block identifiers (Bad Block) of the main area. In x8 devices, the pages in the main area are divided into two half-pages of 256 bytes each, plus 16 bytes of the spare area. On x16 devices, the pages are divided into a 256-word main area and an 8-word spare area.


Fig.5 Organization of NAND-memory array

NAND flash devices with 528 bytes / 264 words pages may contain bad blocks, which may contain one or more invalid cells that are not guaranteed to be reliable. In addition, additional unusable blocks may appear during the operation of the product. Information about bad blocks is written to the crystal before it is sent. Working with such blocks is performed according to the procedure described in detail in the reference manual for Hynix memory chips.

When working with memory chips, three main actions are performed: reading (Fig. 6), writing (Fig. 7) and erasing (Fig. 8).

Data reading procedure


Fig.6 Diagram of the reading procedure

Procedures for reading data from NAND memory can be of three types: random read, page read, and sequential line read. With random reading, a separate command is needed to obtain one portion of data.

The page is read after a random read access, in which the contents of the page are transferred to the page buffer. On the completion of the transfer informs a high level on the output "Read / Busy". Data can be read sequentially (from the selected column address to the last column) by pulsed on the Read Enable (RE) signal.

Sequential read mode is active when the Chip Enable (CE) input remains low and the Read Enable input pulses after the last column of the page has been read. In this case, the next page is automatically loaded into the page buffer and the read operation continues. The sequential line read operation can only be used within a block. If the block changes, a new read command must be issued.

Data recording procedure


Fig.7 Write procedure diagram

The standard procedure for writing data is paging. The main area of ​​the memory array is programmed in pages, however it is possible to program a part of a page with the required number of bytes (from 1 to 528) or words (from 1 to 264). The maximum number of consecutive entries of parts of the same page is no more than one in the main area and no more than two in the spare area. Once these values ​​are exceeded, a clear block command must be issued before any subsequent programming operation on this page. Each programming operation consists of five steps:

  1. One bus cycle is required to set up a page write command.
  2. Four bus cycles are required to transfer an address.
  3. Issuing data to the bus (up to 528 bytes / 264 words) and loading into the page buffer.
  4. One bus cycle is required to issue an acknowledge command to start the PER controller.
  5. The execution of the PER controller writing data to the array.

Block Erase Procedure


Fig.8 Erase procedure diagram

The erase operation is performed at one time on one block. As a result of its operation, all bits in the specified block are set to "1". All previous data is lost. The erasing operation consists of three steps (Fig. 8):

  1. One bus cycle is required to set the block erase command.
  2. Only three bus cycles are needed to set the block address. The first cycle (A0-A7) is not required since only addresses A14 to A26 (higher addresses) are valid, A9-A13 are ignored.
  3. One bus cycle is required to issue an acknowledge command to start the PER controller.

In addition to Hynix, NAND-memory chips are produced by several other manufacturers, among which Samsung has a very large range and sales volume of products. It produces two basic lines of NAND Flash and One NAND™ memory chips. The One NAND™ family of memory modules is a single-chip memory with a standard NOR-flash interface based on an array of NAND-flash cells.

The range of products manufactured by Samsung is wider than that of Hynix. Modules with capacities from 4 Mbps to 8 Gbps are presented, operating in commercial and industrial temperature ranges. Both 8 and 16-bit modifications are available for different supply voltage ranges: 1.65 ... 1.95 V or 2.7 ... 3.6 V. Products manufactured by Samsung have advanced hardware data protection capabilities: write protection for BootRAM, flash array protection mode, and protection against accidental writes when turned on and off.

Otherwise, the design of Hynix memory chips and Samsung's NAND Flash products is almost identical. In this situation, the preferred option for the consumer is the product of the manufacturer whose market value of products is the most acceptable.

High performance when reading serial data streams predetermines a wide scope of applicability of NAND flash. A very popular and promising market for this type of memory is the market solid state drives for the USB bus. Table 3 reflects the capabilities of currently produced NAND-flash chips in relation to this area. In addition, the most advantageous is the use of such memory in MP3 players, digital cameras, computers - handhelds and other similar equipment.

Table 3. Advantages and disadvantages of using NAND flash in solid state drives

Category Content
Opportunities Advantages Data storage that can be transferred via USB
Small size, easy to create portable devices
No memory limit
Secure data storage, physically more reliable than HDD
Support for Plug&Play hot plug function
Fast transmission speed:
USB 1.1: Max. 12 Mbaud, USB 2.0: Max. 480 Mbaud
Excellent compatibility with standardized USB interface
Possibility of power supply from USB port(500 mA, 4.5…5.5 V)
disadvantages Need for software in operating system host controller
The need for a USB host chipset
High cost compared to HDD of comparable capacity
Product capacity 16 Mbps to 8 Gbps
Transmission speed Recording Up to 13 Mbps under USB 2.0 with SanDisk CF card
Reading Up to 15 Mb / s under USB 2.0 from SanDisk
Application PC (desktop, laptop), DVC, PDA, cell phones, etc.
Leading Manufacturers Using Flash Memory M-Systems, Lexar Media, SanDisk, etc.
Associations USB-IF (USB Designers Forum), UTMA (Universal Transportable Memory Association)
The New Year is a pleasant, bright holiday, on which we all sum up the results of the past year, look to the future with hope and give gifts. In this regard, I would like to thank all habr-residents for their support, help and interest in my articles (, , ,). If you had not once supported the first one, there would have been no subsequent ones (already 5 articles)! Thanks! And, of course, I want to make a gift in the form of a popular science and educational article about how fun, interesting and beneficial (both personal and public) can be used, rather harsh at first glance, analytical equipment. Today, on New Year's Eve, on the festive operating table are: a USB-Flash drive from A-Data and a SO-DIMM SDRAM module from Samsung.

Theoretical part

I will try to be as brief as possible so that we all have time to prepare Olivier salad with a margin for the festive table, so part of the material will be in the form of links: if you want, read at your leisure ...
What kind of memory is there?
At the moment, there are many options for storing information, some of them require a constant supply of electricity (RAM), some are permanently "sewn" into the control microcircuits of the technology around us (ROM), and some combine the qualities of those and others (Hybrid). Flash belongs to the latter, in particular. It seems to be non-volatile memory, but the laws of physics are difficult to cancel, and periodically you still have to rewrite information on flash drives.

The only thing that, perhaps, can unite all these types of memory is more or less the same principle of operation. There is some two-dimensional or three-dimensional matrix, which is filled with 0 and 1 approximately in this way and from which we can subsequently either read these values ​​or replace them, i.e. all this is a direct analogue of the predecessor - memory on ferrite rings.

What is flash memory and what is it like (NOR and NAND)?
Let's start with flash memory. Once upon a time, on the notorious ixbt, quite a lot was published about what Flash is, and what 2 main varieties of this type of memory are. In particular, there is NOR (logical not-or) and NAND (logical not-and) Flash memory (everything is also described in great detail), which differ somewhat in their organization (for example, NOR is two-dimensional, NAND can be three-dimensional), but they have one common element - a floating gate transistor.


Schematic representation of a floating gate transistor.

So how does this marvel of engineering work? Together with some physical formulas, this is described. In short, between the control gate and the channel through which the current flows from the source to the drain, we place the same floating gate, surrounded by a thin layer of dielectric. As a result, when current flows through such a “modified” FET, some of the high-energy electrons tunnel through the dielectric and end up inside the floating gate. It is clear that while the electrons were tunneling and wandering inside this gate, they lost some of their energy and practically cannot return back.

NB:“practically” is the key word, because without overwriting, without updating cells at least once every few years, Flash is “zeroed” just like RAM, after the computer is turned off.

Again, we have a two-dimensional array that needs to be filled with 0s and 1s. Since it takes quite a long time to accumulate charge on the floating gate, a different solution is applied in the case of RAM. A memory cell consists of a capacitor and a conventional field effect transistor. At the same time, the capacitor itself has, on the one hand, a primitive physical device, but, on the other hand, it is non-trivially implemented in hardware:


RAM cell device.

Again, ixbt has a good one dedicated to DRAM and SDRAM memory. It is, of course, not so fresh, but the fundamental points are described very well.

The only question that torments me is: can DRAM have, like flash, a multi-level cell? It seems so, but still...

Part practical

Flash
Those who have been using flash drives for a long time have probably already seen a “naked” drive, without a case. But I will still briefly mention the main parts of a USB flash drive:


The main elements of a USB-Flash drive: 1. USB connector, 2. controller, 3. PCB-multilayer printed circuit board, 4. NAND memory module, 5. reference frequency crystal oscillator, 6. LED indicator (now, however, on many flash drives do not have it), 7. a write protection switch (similarly, many flash drives do not have it), 8. a place for an additional memory chip.

Let's go from simple to complex. Crystal oscillator (more on the principle of operation). To my deep regret, during the polishing, the quartz plate itself disappeared, so we can only admire the case.


Crystal oscillator housing

By chance, in the meantime, I found what the reinforcing fiber looks like inside the textolite and the balls that make up the textolite for the most part. By the way, the fibers are still laid with a twist, this is clearly seen in the top image:


Reinforcing fiber inside the textolite (red arrows indicate fibers perpendicular to the cut), of which the bulk of the textolite consists

And here is the first important part of the flash drive - the controller:


Controller. The top image was obtained by combining several SEM micrographs.

To be honest, I didn’t quite understand the idea of ​​​​the engineers who placed some additional conductors in the chip filling itself. It may be easier and cheaper to do this from the point of view of the technological process.

After processing this picture, I shouted: “Yaaaaaaz!” and ran around the room. So, the 500 nm process technology is presented to your attention in all its glory with perfectly traced boundaries of the drain, source, control gate, and even the contacts have been preserved in relative integrity:


"Ide!" microelectronics - 500 nm controller process technology with beautifully traced separate drains (Drain), sources (Source) and control gates (Gate)

Now let's get down to dessert - memory chips. Let's start with the contacts that feed this memory in the truest sense of the word. In addition to the main (in the figure the “thickest” contact) there are also many small ones. By the way, "fat"< 2 диаметров человеческого волоса, так что всё в мире относительно:


SEM images of pins powering the memory chip

If we talk about memory itself, then success awaits us here too. It was possible to shoot individual blocks, the boundaries of which are marked with arrows. Looking at the image with maximum magnification, try to strain your eyes, this contrast is really hard to distinguish, but it is on the image (for clarity, I marked a separate cell with lines):


Memory cells 1. Block boundaries are marked with arrows. Lines represent individual cells

At first it seemed to me as an artifact of the image, but after processing all the photos at home, I realized that these are either control shutters elongated along the vertical axis with an SLC cell, or these are several cells assembled in an MLC. Although I mentioned MLC above, it is still a question. For reference, the "thickness" of the cell (i.e. the distance between the two bright dots in the bottom image) is about 60 nm.

In order not to dissemble - here are similar photos from the other half of the flash drive. Completely similar picture:


Memory cells 2. Block boundaries are marked with arrows. Lines represent individual cells

Of course, the chip itself is not just a set of such memory cells, there are some other structures inside it, the belonging of which I could not determine:


Other Structures Inside NAND Memory Chips
 

DRAM
Of course, I did not cut the entire SO-DIMM board from Samsung, I only “disconnected” one of the memory modules with the help of a building hair dryer. It is worth noting that one of the tips proposed even after the first publication came in handy here - sawing at an angle. Therefore, for a detailed immersion in what he saw, this fact must be taken into account, especially since the cut at 45 degrees made it possible to obtain, as it were, “tomographic” sections of the capacitor.

However, according to tradition, let's start with contacts. It was nice to see what the BGA “chipped” looks like and what the soldering itself is:


"Skol" BGA-soldering

And now it’s time to shout “Ide!” for the second time, as we managed to see individual solid-state capacitors - concentric circles in the image, marked with arrows. It is they who store our data while the computer is running in the form of a charge on their plates. Judging by the photographs, the dimensions of such a capacitor are about 300 nm wide and about 100 nm thick.

Due to the fact that the chip is cut at an angle, some capacitors are cut neatly in the middle, while others have only “sides” cut off:


DRAM memory at its finest

If someone doubts that these structures are capacitors, then you can see a more “professional” photo (though without a scale mark).

The only thing that confused me is that the capacitors are arranged in 2 rows (lower left photo), i.e. it turns out that there are 2 bits of information per 1 cell. As mentioned above, there is information on multi-bit recording, but how applicable and used this technology is in modern industry remains a question for me.

Of course, in addition to the memory cells themselves, there are also some auxiliary structures inside the module, the purpose of which I can only guess:


Other Structures Inside a DRAM Chip

Afterword

In addition to those links that are scattered throughout the text, in my opinion, this review is quite interesting (albeit from 1997), the site itself (and the photo gallery, and chip-art, and patents, and many, many things) and this office, which actually engaged in reverse engineering.

Unfortunately, we could not find a large number of videos on the production of Flash and RAM, so you will have to be content with assembling USB-Flash drives:

P.S.: Once again, Happy New Year of the Black Water Dragon!!!
It turns out strange: I wanted to write an article about Flash one of the first, but fate decreed otherwise. Fingers crossed, let's hope that the next, at least 2, articles (about bio-objects and displays) will be published in early 2012. In the meantime, the seed is carbon tape:


Carbon tape on which the test samples were fixed. I think normal duct tape looks the same.

The article describes 4 Gbit flash memory chips K9K4G08Q0M-YCB0/YIB0, K9K4G16Q0M- YCBO/YIBO, K9K4G08U0M- YCBO/YIBO, K9K4G16U0M-YCB0/YIB0. These microcircuits are used as non-volatile memory in consumer, industrial and computer devices. In digital video and photo cameras, voice recorders and answering machines, these chips are used as memory for image and sound in solid-state flash drives.

Flash memory chips are divided into groups according to supply voltage and architecture (Table 1). In table. 2 shows the pin assignment of flash memory chips.

Table 1

table 2

No. of pins Pin designation (chip type) Pin assignment
29-32; 41-44 I/O(0-7) (K9K4G08X0M-Y) Data input/output. Pins are used to input/output cell addresses, data or commands during read/write cycles. When a chip is not selected, or pins are disabled, they are placed in a high impedance state.
26, 28, 30, 32, 40, 42, 44, 46, 27, 29, 31, 33, 41, 43, 45, 47 I/0(0-15) (K9K4G16X0M-Y)
16 CLE Command commit permission. A high signal level on this pin switches the multiplexers on the I / O inputs in the direction of the command register. The command is written to the register at the edge of the signal WE
17 ALE Address fixing permission. A high signal level at this input switches the multiplexers on the I / O inputs in the direction of the address register. Fold the command into the register is made on the edge of the signal WE
9 CE Chip selection. A low level at the input allows the data reading operation, and a high level, in the absence of any operations, puts the microcircuit into standby mode. During write/erase operations, the high level on this input is ignored.
8 RE Read permission. The input controls the serial data output when data transfer is active on the I/O bus. The data is valid after the fall of the RE signal and some normalized sampling time. The RE signal also increments the column's internal address counter by one.
18 W.E. Recording permission. The input controls writing to the I/O port. Commands, address and data are latched on the edge of WE
19 WP Write lock. The output provides protection against accidental writing/erasing during power-up. The internal programming voltage generator is disabled when the WP pin is active low.
7 R/B Free/busy. The R/B output indicates the state of the chip. A low level indicates that a random access write, erase, or read operation is in progress, and a high level is set when these operations are completed. This open-drain output does not transition to a high impedance state when the chip is not selected or when the outputs are disabled.
38 PRE Read permission at power on. The PRE output controls the auto-read operation performed at power-up. Power-on autoread is enabled if the PRE pin is connected to the VCC pin.
12 VCC Supply voltage
13 VSS General

The K9K4GXXX0M chips have a capacity of 4 Gb with 128 Mb of reserve (actual capacity is 4,429,185,024 bits) and a 512 Mb x 8 or 256 Mb x 16 architecture with up to 1M write/erase cycles reliability. 8-bit chips are organized in 2112 x 8 pages, while 16-bit chips are organized in 1056 x 16 columns. All microcircuits have spare bits located in 128 rows with addresses 2048-2111 for 8-bit microcircuits, or in 64 columns with addresses 1024-1055 for 16-bit microcircuits. To organize data transfer during a page read / write operation between memory cells and I / O ports, these microcircuits have data registers of 2112 bytes in size for an 8-bit microcircuit, or 1056 words for a 16-bit microcircuit and registers connected in series with each other. cache of the appropriate size. The memory array is built from 32 connected cells located on different pages and united by a NAND structure. 32 cells that combine 135168 2I-NOT structures and are located on 64 pages make up a block. A collection of 8- or 16-bit blocks constitutes a memory array.

The read operation is performed page by page, while the erase operation is only block by block: 2048 individually erased 128 KB ps blocks (for 8-bit microcircuits), or 64 Kword blocks (for 16-bit microcircuits). Erasing individual bits is not possible.

Writing a page to the microcircuit is performed in 300 μs, erasing - in 2 ms per block (128 KB for 8-bit microcircuits, or 64 Kwords for 16-bit microcircuits). A byte of data is read from a page in 50 ns.

To record and control data in microcircuits, there is a built-in controller that provides the entire process, including, if necessary, repeating the operations of internal verification and data labeling. The K9K4GXXX0M microcircuits have a system for providing information verification with error correction and culling of erroneous data in real time.

Chips have 8 or 16 multiplex I/O addresses. This solution drastically reduces the number of outputs involved, and allows for subsequent upgrades of devices without increasing their size. Commands, addresses and data are entered at a low level at the CE pin by the fall of the WE signal through the same input / output pins. The input information is written to the buffer registers on the rising edge of the WE signal. The command write enable (CLE) and address write enable (ALE) signals are used to multiplex the command and address, respectively, through the same I/O pins.

Table 3

* Arbitrary input / output of data is possible within one page

In table. 3 shows the control commands of the microcircuits. Submission to the inputs of other hexadecimal (HEX) command codes that are not listed in the table leads to unpredictable consequences, and therefore is prohibited.

To improve write speed when receiving large amounts of data, the onboard controller has the ability to write data to cache registers. When the power is turned on, the built-in controller automatically provides access to the memory array, starting from the first page without entering a command and address. In addition to the improved architecture and interface, the controller has the ability to copy (overwrite) the contents of one memory page to another without accessing external buffer memory. In this case, the data transfer speed is faster than in normal operation, since there are no time-consuming sequential accesses and data entry cycles.

Block culling

Memory blocks in the K9K4GXXX0M chips are defined as invalid if they contain one or more invalid bits that cannot be read unambiguously. Information from invalid blocks is treated as "invalid block information". Chips with invalid blocks do not differ in static and dynamic characteristics and have the same quality level as chips with all the correct blocks. Invalid blocks do not affect the operation of normal blocks because they are isolated from the bit and common supply rail by the selection transistor. The system is designed in such a way that addresses are blocked for invalid blocks. Accordingly, there is simply no access to incorrect bits.

Invalid Block Identification

The contents of all microcircuit cells (except those where information about invalid blocks is stored) with addresses FFh for 8-bit and FFFFh for 16-bit can be erased. The addresses of invalid blocks located in the spare area of ​​the memory array are determined by the first byte for 8-bit chips or the first word for 16-bit ones. The manufacturer guarantees that either the 1st or 2nd page of each block with addresses of invalid cells has data in columns with addresses 2048 (for 8-bit) or 1024 (for 16-bit) that is different from FFh ​​or FFFFh, respectively. Since information about invalid blocks is also erasable, in most cases, erasing the addresses of bad blocks cannot be restored. Therefore, the system must have an algorithm capable of creating a table of invalid blocks, protected from erasure and based on the initial information about bad blocks.

After clearing the memory array, the addresses of these blocks are loaded again from this table. Any intentional erasure of the original information about invalid blocks is prohibited, as it leads to incorrect operation of the system as a whole.

Over time, the number of invalid blocks can increase, so you should periodically check the actual memory capacity by checking the addresses of the invalid blocks against the data in the backup invalid block table. For systems that require high fault tolerance, it is best to provide for the possibility of block-by-block rewriting of a memory array with a comparison of the results with actual data, quickly identifying and replacing blocks of incorrect information. The data from the detected invalid block is transferred to another, normal empty block, without affecting neighboring blocks of the array and using the built-in buffer, the size of which corresponds to the size of the block. For this, commands for block-by-block rewriting are provided.

Fundamentally, memory chips are divided into non-volatile, which do not lose information when the power is turned off, and volatile, the contents of which are considered undefined each time they are turned on. The first of them are designed to store programs, constants, tables and other data that does not change or rarely changes, and are called ROM (Read Only Memory). The latter are designed for temporary storage of data that occurs during the operation of the device, and are called RAM (Random Access Memory). In turn, ROMs are classified according to the method of entering information and the method of erasing it, if such a possibility exists in this class of ROM. The cheapest way to write is mask programming during the manufacturing process of the chip. Memory chips with<прошитой>information - ROM (Read Only Memory) - cannot be reprogrammed, and they are used only in mass production, large serialization and guaranteed error-free text entered. The next type of ROM - PROM (Programmable Read Only Memory) - comes in<чистом>form and provides the user with the opportunity to independently, with the help of the programmer, enter the required content. If this process is irreversible, then such microcircuits are called OTP (One Time Programmable) - once programmable. If it is possible to clear the content and then add a new one, then the chips are called EPROM (Erasable Programmable Read Only Memory). And finally, depending on the erasing method, they can be either UV-EPROM, with ultraviolet erasure, or EEPROM, with electrical erasure. However, the terminology that has developed in recent years more often uses the abbreviation EEPROM for a certain type of memory, which, in a sense, can be considered non-volatile RAM.
Actually ROM with electrical erasure is called Flash memory. The differences between them are quite large. EEPROM allows random access to memory cells during writing, Flash memory assumes only page, that is, divided into sectors, access during erasing/writing. It is impossible to overwrite the contents of a single memory cell. When reading, there is no fundamental difference between them. Besides, flash programming memory is a whole process that requires additional software steps to put the chip into programming mode and control its completion. As a result, the scope of Flash memory is program texts, tables and other data, the change of which is either not expected at all, or is allowed, but very rarely. EEPROM memory is used for the current storage of data during operation, when changing constants, settings (for example, on a TV), with their automatic saving when the power is turned off. At the same time, Flash memory has a larger capacity and a lower price in terms of the cost of storing one byte of information.
RAM (RAM - Random Access Memory) is fundamentally divided into two types: static - SRAM and dynamic - DRAM. The first, in the presence of a supply voltage, can store the recorded information for as long as you like without any calls to it. The storage cell is the trigger. The second requires constant<регенерации>, that is, reading and re-writing to the corresponding cells. This is due to the physical basis of storage, which in DRAM is a capacitor of negligible capacity, connected at the intersection of the rows and columns of the matrix. This achieves an ultra-high packing density and a large specific information capacity of the microcircuit. The price is the need to periodically carry out a regeneration cycle. You also have to sacrifice energy consumption. DRAM chips are used today almost exclusively in computers and other computing technology.
For us, SRAM chips are of greater interest, which, in turn, are divided into micro-power ones with relatively low (55 - 120 ns) speed and high-speed (7 - 25 ns) with significantly higher power consumption.
There are other types of RAM, such as "Zero-Power" with a built-in lithium battery or "Dual-Port" with a different access system than usual.


The main parameters of memory chips:
  • information capacity. The ability to store a certain number of bits of binary information;
  • organization of memory chips. It can be different for the same amount of memory. For example, 65,536 bits might look like 4,096 x 16, or 8,192 x 8, or some combination. The internal organization of the storage matrix remains unchanged, only the external interface and, accordingly, the number of external pins change;
  • sampling time. The time from the last of the signals allowing reading to the appearance of stable data at the output;
  • power consumption. As usual, there is a trade-off between power consumption and chip speed;
  • supply voltage. The general trend towards lower supply voltage has led to the appearance of memory chips operating at 3.3, 2.5 and even 1.8 volts;
  • temperature Range. Commercial, industrial or advanced.
The specific parameters of the memory include such as: storage time(hours, years), number of write cycles, erasing time and others.

In conclusion, it should be noted that EEPROM and Flash type chips often have a serial external data exchange interface. This significantly reduces the exchange rate, but, in those applications where it is not critical, allows you to save the number of external microcircuit pins occupied by printed circuit board area, number of rations.

The article talks about the principles of building memory chips and provides an overview various kinds memory products developed and manufactured by STMicroelectronics, one of the world leaders in the production of electronic components, including memory chips, and which has a unique technology for the production of Flash memory and programmable memory systems on a single chip.

All articles in the series:

1. Types of memory chips from STMicroelectronics

Dear reader! Recently, on the pages of specialized magazines, there are often publications devoted to memory chips from various manufacturers, including review articles. At the same time, when listing manufacturers of memory chips, due attention is not always paid to one of the world leaders in this field - STMicroelectronics. To fill in the gaps in this issue, a series of articles is intended, the first of which is offered to your attention.

Currently, STMicroelectronics (ST) develops and commercially manufactures the following types of memory chips:

  • EPROM - a wide range of UV-erasable, one-time programmable memory, including standard OTP and UV EPROM memory chips, Tiger Range advanced OTP and UV EPROM memory chips, a new type of FlexibleROM memory designed to replace Mask-ROM, and PROM and RPROM memory chips from WSI (USA), which is part of ST;
  • EEPROM and SERIAL NVM (serial non-volatile long-term memory) - EEPROM memory chips with various bus interfaces, serial FLASH memory, standard special-purpose memory chips (ASM) and contactless (CONTACTLESS MEMORIES) memory chips are produced from serial reprogrammable non-volatile memory ;
  • Flash Memory - ST manufactures Flash memory chips: industry standard with various power supplies, Flash memory chips with advanced architecture for various applications, heterogeneous memory chips and Flash memory chips of the "LightFlash" family;
  • SRAM - ST manufactures asynchronous, low power SRAM memory chips in a variety of power and speeds;
  • NVRAM - there are solutions for battery-backed SRAM and time pulse generators (real time clock);
  • PSM - in accordance with the strategic direction of creating "systems on a chip", ST designs and manufactures programmable memory chips that provide a comprehensive system solution memory for microcontrollers and developments on signal processors (DSP);
  • Smartcard - a wide range of chips for Smartcard and security systems is available.

Types and main series of memory chips manufactured by STMicroelectronics are shown in Figure 1.

Rice. 1. Types and main series of memory chips from STMicroelectronics

EPROM, EEPROM and Flash - what's the difference?

The first non-volatile memory technologies were EPROM (Erasable Programmable Read Only Memory) and EEPROM (Electronically Reprogrammable Read Only Memory). In EPROM, data can be written to memory once and subsequently read any number of times. If the EPROM has a special case with a transparent window, then the contents of the memory can be erased by ultraviolet radiation, and then reprogrammed with new data.

EEPROM is more flexible. It provides for multiple reprogramming of memory cells, but the price of this flexibility is a more complex memory cell structure, which increases cost and reduces storage density. For this reason, EPROM is mainly used as a convenient memory for storing large amounts of program code, and EEPROM for storing parameters and other information that needs to be updated regularly.

In recent years, the semiconductor industry has experienced rapid growth in the electronic Flash memory sector, which is increasingly used in many telecommunications, automotive electronics, computers and home appliances, but which few semiconductor manufacturers can produce in industrial volumes and inexpensively for the consumer. .

Flash memory belongs to the class of semiconductor memory with long-term storage (NON-VOLATILE) or non-volatile from external power supply. Prior to its introduction, the most popular types of memory on the market were DRAM (Dynamic Random Access RAM) and SRAM (Static Random Access RAM). Despite their volatility, this is due to the ability to provide high write speeds, which is mandatory for RAM. In addition, the small size of DRAM memory cells allows for high storage densities, which are typically 256 Mb today and up to 1 Gb in the future. SRAM has the advantage of lower overhead and (for some types) faster read speeds - typically an order of magnitude faster than DRAM. DRAM and SRAM are one of the main components of personal computers.

Flash technology was originally used as an EPROM replacement option. Like EEPROM, Flash memory is electrically erasable and has virtually no limit on the number of reprogramming cycles, but unlike EEPROM, Flash memory chips are cheaper to manufacture and can have very large storage capacities. Flash memory, unlike EEPROM, does not need to be completely erased before being overwritten, which gives it an additional advantage. It is usually organized into multiple sectors, each of which can be individually reprogrammed.

The development of Flash memory technology is carried out in two main directions: cell size reduction due to new manufacturing processes (0.25µ, 0.18µ, 0.13µ, 0.10µ ...) and optimization of the memory architecture for specific applications. Compared to DRAM, Flash memory is more difficult to design and manufacture. Therefore, its development in density lags behind DRAM by about one gradation. That is, if DRAM is produced using 0.18µ technology, then Flash memory will be produced using 0.25µ technology.

In pursuit of ambitious goals, ST began to develop and manufacture Flash memory using new technologies at a faster pace in order to align its technology with DRAM technology. For the same purpose, a Center was established in Agrate (Italy). The company's hopes to produce Flash with a memory density as good as DRAM is based on the implementation of multi-bit cell techniques. Therefore, in the near future, we should expect the appearance of Flash-memory chips with a capacity of up to 1 Gbit.

The second approach that ST is successfully pursuing is the development of special-purpose microcircuits with architectures that are as optimized as possible for specific operating conditions. Much here depends on close cooperation with leading manufacturers of modern electronic equipment and trends in its development. In this area, ST has a significant advantage over other flash memory manufacturers, especially in the field of computer peripherals, communications and automotive electronics.

The rapid growth in the use of Flash-memory is due to the rapid development of electronic devices and is objective. For example, in the cell phone market, Flash-memory chips with a small capacity (1...4 Mb) were first used to store the code. Then the functionality of cell phones exploded to provide the Internet, GPS, interactive news feeds, television conferencing, and CD music. Each new service function requires an increase in the amount of Flash-memory for storing code, the capacity of which has increased to 128 MB during this time. Now a cell phone is equipped with a camera, a biometric sensor, the ability to download music and programs. This means that if now for cell phone Basically, it is enough to have 8 MB of Flash-memory, then by the end of 2004 the possibilities available today in 128 MB of Flash-memory will be fully utilized.

More importantly, standard Flash chips are not the best choice for these products. The mutually exclusive needs for maximizing performance, reducing cost and power consumption can only be partially met and applied to a particular cellular telephone application.

Similar growth can be predicted for various kinds of set-top boxes and for the DVD market. And here, in order to meet the needs and requirements of this market, which is especially sensitive to cost and quality characteristics, you need a specialized Flash memory with an architecture optimized for this market (for example, x32 architecture with two memory banks and 100 MHz group read characteristics), which will be used rather than standard Flash memory chips.

Staying ahead of the market has helped STMicroelectronics develop new products such as ultra-fast (25 ns!) access times in Flash memory chips for computer hard disks and the world's first 32Mb Flash memory that combines dual-bank memory architecture and fast access. with full-featured 1.8V paging mode for the next generation of cell phones.

Flash, EPROM, and EEPROM use the same basic floating-gate mechanism for storing data, but different methods for writing and reading data. In each case, the basic memory cell consists of one MOSFET with two gates: a regulator transistor, which is connected to the read-write control circuit, and a floating one, which is located between the regulator gate and the MOSFET channel (the part of the MOSFET between source and drain). ). The basic EPROM cell diagram is shown in Figure 2.


Rice. 2. Basic EPROM cell

Unlike a standard MOSFET, memory chips have two gates that are completely electrically isolated by a layer of silicon dioxide from the rest of the electrical circuit. Since the floating gate is physically very close to the channel of the MOSFET, even a very small electrical charge on it affects the electrical resistance of the transistor. By applying the appropriate signals to the control gate, and by measuring the change in the resistance of the transistor, it is possible to determine the presence electric charge on a floating gate. Because the floating gate is electrically isolated from the rest of the circuit, special methods are required to transfer charge across it. One method is to flood the channel of the MOSFET with high energy electrons by applying a relatively high voltage to the gate and drain of the MOSFET. Some of these "hot" electrons have enough energy to cross the potential barrier between the channel and the floating gate. When withdrawing high voltage they remain trapped by the floating gate. Namely, this method is used to program a memory cell in EPROM and Flash memory.

This technique, known as hot electron channel injection (CHE), can be used to transfer charge to the floating gate, but it does not reset the charge. EPROM technology achieves this by exposing the entire memory array to ultraviolet light, which gives the trapped electrons enough energy to exit the floating gate. This is a fairly simple and effective method of erasing.

The second method of charge removal is based on the use of the so-called tunnel effect. The electrons leave the floating gate when a sufficiently high voltage is applied to the source of the MOSFET, which causes the electrons to "tunnel" across the insulating oxide film to the source. The number of electrons that can tunnel across the insulating layer in a given time depends on the thickness of the layer and the magnitude of the applied voltage. For realistic voltage levels and limited erasing times, the insulating layer must be very thin - typically 10 nm (100 Angstroms).


Rice. 3. Basic EEPROM cell

In EEPROM memory chips, the tunnel effect is used to "charge" and "discharge" the floating gate according to the polarity of the applied tunnel voltage (Figure 3). Therefore, although Flash technology is not just a grafting of the EEPROM erasing mechanism onto EPROM technology, Flash memory can be thought of as a storage device that is programmed like EPROM and erased like EEPROM.

The most significant difference between EPROM and the other two types of memory is the thickness of the oxide film that separates the floating gate from the source. In EPROM, this is usually 20 ... 25 nm, and this is quite a lot to implement the tunnel effect at practical voltages. Flash memory (Figure 4) has a tunnel oxide film thickness of 10 nm, and its quality has a significant impact on the performance and reliability of the memory chip. This is one of the main reasons why relatively few electronics manufacturers have mastered Flash memory technology, and even fewer are able to reliably combine Flash technology with other CMOS components to create products such as microcontrollers with embedded Flash memory.

Traditionally, the floating gate was used to store a single data bit, which was read by comparing the MOSFET threshold voltage with a reference value, but more sophisticated read-write methods have emerged that allow more than two floating gate energy states to be distinguished, which is equivalent to storing two and more bits on a single floating gate. This is a major scientific and technological achievement, because storing two bits in one cell allows you to double the capacity of memory chips without changing their physical size. STMicroelectronics is one of the few companies that can offer flash memory chips with a multi-bit cell architecture.


Rice. 4. Basic cell Flash

Although all Flash memory chips use the same basic storage cell, there are many types of their connections within the entire memory matrix. The most famous architectures are NOR (NOT) and NAND (NAND). These conditions of traditional combinatorial logic determine the topology of the memory matrix and the types of connection to individual cells when accessing them for reading and writing.

Initially, there was a clear difference between these two fundamentally different architectures. NOR devices exhibited significantly faster read times (providing better code storage capabilities), while NAND devices offered higher storage densities (because a NAND cell is about 40% smaller than a NOR cell). However, the advent of multi-bit cell technology shifts the balance explicitly towards NOR architectures. In addition, it should be taken into account that in the NOR architecture, the signal readout amplifiers have direct access to each memory cell, and in the NAND architecture, the readout amplifier signal must pass through many other cells, each of which can introduce a certain error. Therefore, it is unlikely that the NAND circuit can be with a two-bit memory cell, and for the NOR architecture, a four-bit cell should be expected soon and its advantage will finally be established.

2. ST EPROMs

STMicroelectronics (ST) manufactures highly competitive EPROM memory chips. Continuous improvements in manufacturing technology lead to their expansion of capabilities, higher capacity and lower supply voltage. The company is among the world's leading manufacturers of UV-erasable OTP and EPROM memory, which is convenient for development, production and mask ROM replacement due to the fact that they are programmed at the end of production.

The manufactured microcircuits have a capacity from 64 kbps to 64 Mbps with a power supply of 5 and 3 V, sufficient speed, various packages, including those for surface mounting. Device memory organization can be x8, x16 and x8/x16. Deciphering the designations of ST memory chips of the type OTP and UV EPROM is shown in Fig.5.


Rice. 5. Marking of EPROM ST chips

The product portfolio includes standard 5V and 3.3V ICs, advanced Tiger Range 3V (2.7…3.6V) ICs, and the new FlexibleROM™ family.

These memory types are available in FDIP ceramic windowed and PDIP plastic double-row packages, as well as surface mount PLCC and TSOP packages. The main parameters of standard EPROM memory chips are shown in Table 1.

Table 1. OTP and UV EPROM

Volume Designation Description Frame
Power supply 5 V
64 kb M27C64A 64 kb (x8), 100 - 200 ns FDIP28W, PLCC32
256 kb M27C256B 256 kb (x8), 45 - 150 ns
512 kb M27C512 512 kb (x8), 45 - 150 ns FDIP28W, PDIP28, PLCC32, TSOP28
M27C516 512 kb (x16), 35 - 100 ns PLCC44, TSOP40B
1 MB M27C1001 1 MB (x8), 35 - 150 ns
M27C1024 1 MB (x16), 35 - 150 ns
2 MB M27C2001 2 MB (x8), 35 - 100 ns FDIP32W, PDIP32, PLCC32, TSOP32A
M27C202 2 MB (x16), 45 - 100 ns FDIP40W, PDIP40, PLCC44, TSOP40B
4 MB M27C4001 4 MB (x8), 35 - 150 ns FDIP32W, PDIP32, PLCC32, TSOP32A
M27C4002 4 MB (x16), 45 - 150 ns
M27C400 4 MB (x8/x16), 50 - 100 ns FDIP40W, PDIP40
8 MB M27C801 8 MB (x8), 45 - 150 ns FDIP32W, PDIP32, PLCC32, TSOP32A
M27C800 8 MB (x8/x16), 50 - 120 ns
16 MB M27C160 16 MB (x8/x16), 50 - 120 ns FDIP42W, PDIP42, PLCC44, SO44
32 MB M27C322 32 MB (x16), 50 - 100 ns FDIP42W, PDIP42, PSDIP42
M27C320 32 MB (x8/x16), 50 - 100 ns TSOP48, SO44
64 MB* M27C642 64 MB (x16), 80 - 100 ns FDIP42W, PDIP42
M27C640 64 MB (x8/x16), 80 - 100 ns TSOP48
Power supply 3.3V
16 MB M27V160 16 MB (x8/x16), 100 - 150 ns FDIP42W, PDIP42, SO44
32 MB M27V322 32 MB (x16), 100 - 150 ns FDIP42W, PDIP42

* in developing

Advanced Low Voltage Tiger Range

For the low voltage Tiger Range series, STMicroelectronics used latest technology OTP and UV EPROM. Structural improvements related to the thickness of the base layers have made it possible to significantly improve electrical characteristics. A 25% reduction in the thickness of the gate oxide layer made it possible to lower the cell threshold voltage and increase the sampling rate when powered from 2.7 V and higher over the entire temperature range from -40 to +85°C.

While improving electrical performance, ST strives to provide consumers with products with new qualities and therefore recommends customers to replace the "V" series with a power supply of 3 ... 6V. Timing for the Tiger Range series is guaranteed by double testing the chips at 2.7V and 3V. The access time at 2.7V is marked on the chip and faster access times are specified in the description.

Access times for supply voltages above 2.7 V are valid. The composition of the Tiger Range family of chips is shown in Table 2.

Table 2. Tiger Range OTP and UV EPROM, 3V Supply

Volume Designation Description Frame
256 kb M27W256 256kb (x8), 80ns (70ns/3V) - 100ns FDIP28W, PDIP28, PLCC32, TSOP28
M27W512 512kb (x8), 80ns (70ns/3V) - 100ns FDIP28W, PDIP28, PLCC32, TSOP28
1 MB M27W101 1MB (x8), 80ns (70ns/3V) - 100ns FDIP32W, PDIP32, PLCC32, TSOP32A
M27W102 1Mb (x16), 80ns (70ns/3V) - 100ns FDIP40W, PDIP40, PLCC44, TSOP40B
2 MB M27W201 2MB (x8), 80ns (70ns/3V) - 100ns FDIP32W, PDIP32, PLCC32, TSOP32A
M27W202 2 MB (x16), 100 ns (80ns/3V) FDIP40W, PDIP40, PLCC44, TSOP40B
4 MB M27W401 4MB (x8), 80ns (70ns/3V) - 100ns FDIP32W, PDIP32, PLCC32, TSOP32A
M27W402 4MB (x16), 100ns (80ns/3V) - 120ns FDIP40W, PDIP40, PLCC44, TSOP40A
M27W400 4MB (x8/x16), 100ns (80ns/3V) - 120ns FDIP40W, PDIP40, PLCC44
8 MB M27W801 8 MB (x8), 100 ns (80ns/3V) - 120 ns FDIP32W, PDIP32, PLCC32, TSOP32A
M27W800 8MB (x8/x16), 100ns (90ns/3V) FDIP42W, PDIP42, PLCC44

The UV and OTP EPROM Tiger Range family is characterized by ultra-low power consumption, high speed and at the same time fast access with short programming time. Chip programming time is the same for both word and byte programming modes. For the latest chips with a density of 4 MB and 8 MB, the programming speed has been increased to 50 µs per word or byte. The consumption and performance data of the Tiger Range series are shown in Table 3.

Table 3. Tiger Range

Designation Volume (Organization) Consumption Sample rate Programming speed
M27W256 256 kb (x8) 15mA at 5MHz 80ns (70ns/3V) 100 µs/byte
M27W512 512 kb (x8) 15mA at 5MHz 80ns (70ns/3V) 100 µs/byte
M27W101 1 MB (x8) 15mA at 5MHz 80ns (70ns/3V) 100 µs/byte
M27W102 1 MB (x16) 15mA at 5MHz 80ns (70ns/3V) 100 µs/word
M27W201 2 MB (x8) 15mA at 5MHz 80ns (70ns/3V) 100 µs/byte
M27W202 2 MB (x16) 20mA at 5MHz 100ns (80ns/3V) 100 µs/word
M27W401 4 MB (x8) 15mA at 5MHz 80ns (70ns/3V) 100 µs/byte
M27W402 4 MB (x16) 15mA at 5MHz 100ns (80ns/3V) 100 µs/word
M27W400 4 MB (x8/x16) 20mA at 8MHz 100ns (80ns/3V) 50 µs/word
M27W801 8 MB (x8) 15mA at 5MHz 100ns (80ns/3V) 50 µs/byte
M27W800 8 MB (x8/x16) 30mA at 8MHz 100ns (90ns/3V) 50 µs/word

The low voltage Tiger Range ICs are fully pin compatible with the standard 5V UV and OTP EPROM series. This ensures that they are fully compatible for applications where microprocessor power is changed from 5V to 3V (Table 4).

Table 4. UV and OTP EPROM Power Compatibility

3 V Designation Volume (Organization) 5 V Designation
M27W256 256 kb (x8) M27C256B
M27W512 512 kb (x8) M27C512
M27W101 1 MB (x8) M27C1001
M27W102 1 MB (x16) M27C1024
M27W201 2 MB (x8) M27C2001
M27W202 2 MB (x16) M27C202
M27W401 4 MB (x8) M27C4001
M27W402 4 MB (x16) M27C4002
M27W400 4 MB (x8/x16) M27C400
M27W801 8 MB (x8) M28C801
M27W800 8 MB (x8/x16) M27C800

The trend towards higher memory densities has continued for many years. In response to customer requirements, ST is constantly developing both its production technologies and the components themselves.

The flexibility of EPROM, its lower manufacturing costs and the ability to be programmed at the end of production means that many customers now prefer to use this kind of memory instead of mask ROM. The EPROM ST memory range includes many types of chips that can easily be used in place of mask ROM (Table 5).

Table 5. Replacing the Mask ROM with a high-density EPROM

Designation Organization Sample rate Consumption
Power supply 5 V
M27C801 x8 45 ns 35 mA at 5 MHz
M27C800* x8/x16 50 ns 70 mA at 8 MHz
M27C160* x8/x16 50 ns 70 mA at 8 MHz
M27C322* x16 50 ns 50 mA at 5 MHz
M27C320* x8/x16 50 ns 70 mA at 8 MHz
Power supply 2.7 V (min)
M27W801* x8 100 ns (80 ns/3V) 15 mA at 5 MHz
M27W800* x8/x16 100 ns (90 ns/3V) 30 mA at 8 MHz

* replacing Mask ROM

As an example, let's take a closer look at the 32 Mbit M27C320 (4M x 8 or 2M x 16) chip, which is mainly intended for slot machines, DVD players and many other applications where microprocessor systems require a lot of memory for data or program codes.

Logic diagram this device shown in fig. 6, and operating modes are presented in table 6. Reading mode requires one supply voltage. All inputs are TTL compatible with the exception of Vpp and A9 12V for IC maker signature.


Rice. 6. M27C320 logic diagram

Table 6. M27C320 Modes of Operation

M27C320 has two kinds of reading mode - word and byte. The type of reading is determined by the signal level at the BYTE pin. When this pin is high, word reading is selected and Q15A-1 is used to output data on Q15. When the signal is low, BYTE is set to byte read mode and pin Q15A-1 is used to address the input on A-1.

The M27C320 has two control functions and both must be logically active in order to receive data at the outputs. In addition, the type of reading by words or by bytes must be selected. Output E is used for device selection and consumption control. The blocking output (G) controls the output and is used to control the reading from the data cell to the output pins regardless of the device selection.

The M27C320 has a standby mode where the power consumption is reduced to 50 - 100 uA. The M27C320 enters this mode when input E is logic high. In standby mode, all outputs are high impedance regardless of input G.

Because EPROMs are typically used in large arrays of memory, these circuits have a dual-line control feature that allows multiple device memory to be accessed. This feature in the M27C320 saves memory space and prevents conflicts when accessing the memory of multiple devices.

Since EPROMs typically operate with transient voltage transients in power circuits, it is recommended that each circuit use a 0.1uF ceramic capacitor between Vcc and Vss and one 4.7uF electrolytic capacitor between Vcc and Vss for each circuit to smooth current. eight chips. This capacitor must be installed near the power connection point on the board.

In the supplied M27C320 chips, all memory cells are in the "1" state. Data is entered by selectively programming "0" at the required bit locations. Only zero is programmed, but both ones and zeros can be present in the data word. The M27C320 is in programming mode with Vpp at 12.5V, G is logic high (Vih), and E is pulsed logic low (Vil).

The programmed data is sent in parallel 16 bits to the data output pins. In programming mode, the signal levels for addressing and input data must correspond to TTL logic, and the supply voltage Vcc must be within 6.25 V ± 0.25 V.

The PRESTO III programming algorithm provides programming of the entire array with a guaranteed time up to 100 s. The programming of a word is carried out by a sequence of pulses of 50 µs per word with a check.

It is possible to program several M27C320s in parallel with different data. This uses a high logic signal at input E to disable programming. Programming is checked by reading. There is a mode of access to the electronic signature of the manufacturer. More detailed information is given in the description of the microcircuit.

ST's EPROM technology is constantly being improved. New perspectives are opening up with the introduction of a new memory chip architecture based on the use of multi-bit memory cells to achieve high recording densities, starting from a capacity of 64 Mbit. In addition, each new development contains several photolithographic innovations that improve the electrical performance of microcircuits.

With the entry into STMicroelectronics of WAFERSCALE INC. (USA) opened up the possibility of supplying memory chips of the PROM (programmable ROM) / RPROM (re-programmable ROM) type. The main parameters of the family of high-performance PROM and RPROM memory chips made using WSI CMOS technology are shown in Table 7. These chips are available in three operating temperature ranges: commercial (from 0 to +70°C), industrial (from -40 to +85°C ) and military (from -55 to +125°C). In addition, some components are manufactured according to the military standard (SMD), including EPROM (Table 8).

Table 7. WSI CMOS PROM/RPROM

Designation Description Corps
WS57C191C 16 kb (2 kb x 8), 25 - 55 ns CERDIP24, 0.6"; PLDCC28; PDIP24, 0.6"
WS57C291C 16 kb (2 kb x 8), 25 - 55 ns PDIP24, 0.3"; CERDIP24, 0.3"
WS57LV291C 16 kb (2 kb x 8), 70 - 90 ns CERDIP24, 0.3"
WS57C45 (order) 16 kb (2 kb x 8), 25 - 45 ns CERDIP24, 0.3"; PDIP24, 0.3"; CERDIP24, 0.3"
WS57C43C 32 kb (4 kb x 8), 25 - 70 ns CLLCC28; CERDIP24, 0.6"; PLDCC28; PDIP24, 0.3"; CERDIP24, 0.3"
WS57C49C 64 kb (8 kb x 8), 25 - 70 ns CLLCC28; CERDIP24, 0.6"; Ceramic Flatpack24; PLDCC28; CLDCC28; PDIP24, 0.3"; CERDIP24, 0.3"
WS57C51C 128 kb (16 kb x 8), 35 - 70 ns
WS57C71C 256 kb (32 kb x 8), 35 - 70 ns CLLCC32; CERDIP28, 0.6"; PLDCC32; CLDCC32; CERDIP28, 0.3"

Table 8. Military EPROM

Designation Description Corps
WS57C128FB 128 kb (16 kb x 8), 35-70 ns CLLCC32; CERDIP28, 0.6"; PLDCC32; CLDCC32
WS57C256F 256 kb (32 kb x 8), 35-70 ns CLLCC32; CERDIP28, 0.6"; PLDCC32; CLDCC32; PDIP28 0.6"; CERDIP28, 0.3"
27C010L 1 Mb (128 kb x 8), 35 - 200 ns CERDIP32, CLLCC32

STMicroelectronics' latest EEPROM development is the FlexibleROM™ family, which can be used as a simple replacement for any ROM. This one-time programmable family, manufactured using ST's 0.15 µm technology, is available to the consumer with an initial memory capacity of 16 Mbit. The new family of memory chips "FlexibleROM" refers to the type of non-volatile memory and is designed to store program code. "FlexibleROM" - ideal for use instead of mask ROM (MaskROM) and transition from Flash-memory to ROM after debugging the program, if you do not plan to change the program code in the future.

These memory chips are optimized for program code storage and can be used in game consoles, DVD players and TV boxes, as well as office automation devices and computer peripherals.

The FlexibleROM family is well-equipped to replace the mask ROM and deliver customer benefits through flexibility and cost of upgrading. The main characteristics of microcircuits of this family are shown in Table 9.

Table 9. FlexibleROM family

The ICs are available in both "blank" and pre-programmed versions. The available possibility of preliminary programming allows the consumer to reduce the time of the production cycle. For example, compared to a mask ROM, time savings of up to two weeks can be achieved when using client code programming during chip fabrication.

Thanks to the flash-based technology, the programming time is also significantly reduced. The FlexibleROM chips are provided with a generic high data rate verbose program capability, allowing a 64Mb device to be programmed in as little as nine seconds.

Another benefit over other One-Time-Programmable ROMs is high programming throughput, as 100% of the functionality of the memory array is verified during testing.

The FlexibleROM memory chips use 2.7V to 3.6V for read operations and 11.4V to 12.6V for programming. The devices are organized as x16-bit, and the default memory mode is set to "Read" at power-up, so they can be read as ROM or EPROM.

Samples M27W016 (DIL or SM package) and M27W064 (SM package) are currently available and mass production has already begun. Production of the M27W032 (SM package) is under way, with 128Mbit and 256Mbit versions planned for production in late 2003.

The main features of "FlexibleROM" memory:

  • Standard set of commands.
  • Standard mask ROM pinout.
  • Standard mask ROM packages.
  • Complete testability in programming.
  • Direct replacement for any ROM.
  • Very fast programming (30 times faster than standard OTP).
  • Custom coding is faster than mask ROM (1-2 weeks).
  • Free preprogramming service.
  • More efficient in use than ROM and OTP.
  • Ability to quickly "in the system" one-time programming.
  • Easy to upgrade memory capacity.

In conclusion overview UV and OTP EPROM memory chips, we present some data on the correspondence of chips of this type from ST company with memory chips from other manufacturers (Table 10).

Table 10. EPROM Crosstab

AMD ST
Am27C128 57C128FB
Am27C256 57C256F
Am27H256 57C256F
ATMEL ST
AT27C010/L 27C010L
AT27HC256/L 57C256F
AT27HC256R/R 57C256F
CYPRESS ST
CY7C261 57C49C
CY7C263 57C49C
CY7C264 57C49C
CY7C271 57C71C
CY7C274 57C256F
CY7C291 57C291C
CATALYST ST
CAT27128A 57C128FB
CAT27256 57C256F
CAT27HC256 57C256F
HITACHI ST
HN27C256HG 57C256F
INTEL ST
27C128B 57C128FB
27C256 57C256F
MICROCHIP ST
27HC256 57C256F
OKI ST
MSM27C256 57C256F
SANYO ST
LA7620 57C64F
SGS-T ST
M27128/A 57C128FB
M27256 57C256F
SHARP ST
LH57126 57C128FB
SIGNETICS ST
27HC128 57C128FB
TI ST
TMS27C128 57C128FB
TOSHIBA ST
TMM27128` 57C128FB
TMM27256 57C256F

Other types of ST memory chips will be considered in future issues of the magazine.

Literature:

  1. Data sheet M27C320, STMicroelectronics, 2000

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